1. Field of the Invention
The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device and method of manufacture which reduces mismatch driven stresses and deflections between interconnect layers.
2. Background Description
To fabricate microelectronic semiconductor devices such as an integrated circuit (IC), many different layers of metal and insulation are selective deposited on a silicon wafer. The insulation layers may be, for example, silicon dioxide, silicon oxynitride, fluorinated silicate glass (FSG) and the like. These insulation layers are deposited between the metal layers, i.e., intermetal dielectric (IMD) layers, and may act as electrical insulation therebetween or serve other known functions. These layers are typically deposited by any well known method such as, for example, plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD) or other processes.
The metal layers are interconnected by metallization through vias etched in the intervening insulation layers. To accomplish this, the stacked layers of metal and insulation undergo photolithographic processing to provide a pattern consistent with a predetermined IC design. By way of example, the top layer may be covered with a photo resist layer of photo-reactive polymeric material for patterning via a mask. A photolithographic process using either visible or ultraviolet light is then directed through the mask onto the photo resist layer to expose it in the mask pattern. An antireflective coating (ARC) layer such as polyimide may be provided at the top portion of the wafer substrate to minimize reflection of light back to the photo resist layer for more uniform processing. The etching may be performed by anisotropic or isotropic etching as well as wet or dry etching, depending on the physical and chemical characteristics of the materials. Regardless of the fabrication process, to maximize the integration of the device components in very large scale integration (VLSI), it is necessary to increase the density of the components.
Although silicon dioxide material has been used as an insulating material due to its thermal stability and mechanical strength, in recent years it has been found that better device performance may be achieved by using a lower dielectric constant material. By using a lower dielectric constant material, a reduction in the capacitance of the structure can be achieved which, in turn, increases the device speed.
The use of organic low-k dielectric materials such as, for example, SiLK (manufactured by Dow Chemical Co., Midland, Mich.) for semiconductor interconnect isolation tend to have a higher coefficient of thermal expansion (CTE) and lower mechanical strength than conventional dielectric materials such as, for example, silicon oxide. By building a hybrid oxide/low-k dielectric stack, where the via levels are fabricated in oxide (e.g., FSG) and the wiring levels are fabricated in low-k material (e.g., SiLK), the large intralevel line-to-line component of wiring capacitive coupling is reduced, thus maximizing the positive benefit of the low-k material while improving the overall robustness and reliability of the finished structure. The hybrid oxide/low-k dielectric stack structure is much more robust than an “all low-k” dielectric stack, which is known to be relatively more susceptible to via resistance degradation or via delamination due to thermal cycle stresses driven by the high CTE of organic and semi-organic low-k dielectrics.
Nonetheless, even with a hybrid oxide/low-k dielectric stack structure, large regions of low-k dielectric (i.e., lateral extents on the order of about ten times the metal film thickness) without any interconnects tend to expand and contract vertically due to its response to increases and decreases in the ambient temperature, respectively. The expansion and contraction of the low-k dielectric causes the adjacent oxide layers to deflect, thus creating feature-dependent stress concentrations at interconnects/vias, especially at the edges of the large regions. Any interconnect/via connections in these edge regions are susceptible to resistance shifts and via opens due to repeated deflections from thermal cycling during manufacture, reliability stressing, and use. For a large enough deflection, a via can separate from the interconnect which it was attached causing a very large increase in resistance or a persistent electric open.
Currently, there are no known methods to increase the strength and robustness of the structure. For example, dummy fill shapes are known in the industry for use in silicon oxide dielectric based structures but in these structures, the dummy fill shapes are used for processing purposes such as to prevent undulations in the upper layer of the structure during planarization processes. These dummy fill shapes do not prevent delamination or add strength to the structure as evidenced by the placement of these structures within the interconnect layer. For example, it is known that dummy fill shapes, as they are presently used in the industry, are deliberately placed away from any metal lines due to the relative difficulty in obtaining the proper manufacturing tolerances. In fact, the standard use of the dummy fill shapes was intended to be used with dielectric materials which had a higher strength than the dummy metal fill shapes, themselves. This, of course, could not then provide any additional strength to the structure.